Bridging Parallel and Reconfigurable
Computing with
Multilevel PGAS and SHMEM+
Reconfigurable computing (RC) systems based on FPGAs are
becoming an increasingly attractive solution to building parallel
systems of the future. Applications targeting such systems have
demonstrated superior performance and reduced energy
consumption versus their traditional counterparts based on
microprocessors. However, most of such work has been limited to
small system sizes. Unlike traditional HPC systems, lack of
integrated, system-wide, parallel-programming models and
languages presents a significant design challenge for creating
applications targeting scalable, reconfigurable HPC systems. In
this paper, we introduce and investigate a novel programming
model based on Partitioned Global Address Space (PGAS), which
simplifies development of parallel applications for such systems.
To read the full paper, please click here:
FPGA based accelerator breaks new ground in Bioinformatics
PROBLEM: The act of aligning DNA, RNA, or protein sequences in order to identify regions of similarity is one of the most common and important tasks in computational biology.
CETIC Research Project in the field of microelectronics entitled as CANAPE .
This paper presents the results of the CANAPE project. The main objectives of this project are to study and to develop a prototype of FPGA based Hardware accelerator.
A 13 Weeks project in just 1 week, for less than $2K.
The goal of the project was to build a custom piece test equipment (system simulator) for a complex system.
The PROC board allows you to concentrate your efforts on the the application since the PCI interface,targeted application driver,
SDRAM interface board design for the latest Altera FPGAs and prototyping PCB(Printed Circuit Board) have been already implemented for you.
Record-Breaking - 1 day with PROC Board does more than 256 PCs * 14 days.
Application: Real-Time Simulator for a Powerful Error-Correcting Code.
This paper was published by Tong Zhang from Rensselaer Polytechnic Institute, Troy, NY.
The fastest real time LDPC decoding simulator ever reported in the open resource based on ProcSuperStar
Platform, was successfully implemented by researchers at Rensselaer VLSI System
Architecture Laboratory. The real-time LDPC decoding simulator achieved an average decoding throughput of 1Gbps with
frame error rate of less than 10-6 by simulating 8x1013 bits within only one day.
Compared to Researchers at Japan AIST which employed Super Cluster of 256 3GHz Processors to simulate 2x1013 bits in two weeks.
Hardware-accelerated protein identification for mass spectrometry.
An ongoing issue in mass spectrometry is the time it takes to search DNA
sequences with MS/MS peptide fragments (see, e.g., Choudary et al.,
Proteomics 2001; 1: 651-667.) Search times are far longer than spectra
acquisition time, and parallelization of search software on clusters requires
doubling the size of a conventional computing cluster to cut the search time in
half. Field programmable gate arrays (FPGAs) are used to create
hardware-accelerated algorithms that reduce operating costs and improve search
speed compared to large clusters.
A Dynamically Reconfigurable Processor for Dataflow Graph Execution.
This paper was presented by Lorenzo Verdoscia from the Research Center on Parallel Computing and Supercomputing - CNR.
The project was implemented using PROC Board hardware.
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