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Proce

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Overview

Gidel ProceTM boards provide FPGA-based platforms for high-speed data acquisition systems, for vision systems, DSP applications and powerful reconfigurable computing. The FPGA, the memory and the daughterboards' flexible architecture (system I/O, DSP etc.) of the Proce system, enable the user to build complex designs at affordable price.
ProceTM  combined with the Proc developer's kit and the Proc_HILs option, improves the project time-to-market. There is no need to design:

  • boards
  • a PCI driver or an application driver layer
  • define board constraints
  • design memory controller or write host interface code

Designers can focus on their proprietary value-added design instead of spending their valuable time to recreate standard design components. With the ProcMultiPortTM, ProcMegaFIFOTM, ProcMegaDelayTM, innovative memory controller, the generated HDL code enables high speed, easy-to-use parallel access to large memories. Proce daughter boards (PSDBs) enables users to achieve system connectivity with the Proce board.

Off-the-shelf PSDBs as CameraLink, DVI and network interfaces, as well as general I/Os and DSPs can be used. Users can build a unique PSDB with dedicated system requirements.

Key Features

  • Altera Stratix II 60 to 180 FPGA.
  • Up to 179400 logic elements.
  • PCI Express x4 lanes with full duplex operation.
  • 8 DMA channels.
  • Five level memory structure (over 4 GB):
    • Up to 930 M512 RAM blocks (32 x 18 bits).
    • Up to 768 M4K RAM blocks (128 x 36 bits).
    • Up to 9 MegaRAM blocks (4K x 144 bits).
    • 2 DDR II SODIMMs up to 2GB each. With up to 4.8 GB/s sustain access. (Access of up to 32 ports in parallel).
    • Up to 8GB on a PSDB_Mem2. (Access of up to 16 ports in parallel).
  • Unique DDR memory controller enables innovative algorithm designs.
  • Up to 3 TMS320C6414-1GHz DSPs on a PSDB_DSP1G daughter board, with 64MB memory per DSP.
  • Up to 3 PSDBs (Proce Daughter Boards): CameraLink, PSDB_IO and other functions.
  • Up to 314 available I/Os.
  • Flexible clocking system.
  • Typical system frequencies: 100 - 300MHz. ProcMegaFIFOTM
  • Supported by Gidel ProcDeveloper's Kit and Gidel HILDeveloper's Kit.
Benefits

  • High performance.
  • Maximum flexibility to fit your algorithm needs.
  • Cuts project development cycle time and budget
  • Improve system reliability.
  • Improve system maintainability.
  • Long life cycle.
  • Affordable pricing.

    Application examples

  • Powerful frame grabber.
  • Vision, imaging and image recognition.
  • DSP.
  • System hardware acceleration.
  • Aerospace and military systems.
  • Algorithm design and verification .
  • Rapid prototyping.


  • Operating systems

  • Microsoft Windows.
  • Linux.


  • Development Environment

    The ProcWizard initializes the hardware and automatically generates the:

    • C++ class application driver
    • Top-level designs and the interface modules / entities
    • Device constraints (as pin-outs and pin drive)
    • Interface documentation in HTML or Microsoft Word

    The ProcMultiPort core provides two basic benefits:

    • Simplifies achieving high system performance
    • Replaces the need for inventory of special memories with standard memory and IP

    The ByteBlaster via SignalTap or Identify, enable visibility of internal nodes using the available on-chip memory.

    The PSDB_Proto daughter board includes a prototyping area that enables rapid system additions by wiring/soldering devices & connectors. Logic analyzer connections are placed on the daughter board for easy debugging.


    Ordering Codes

    See the ordering codes for Proce here


    Proc Boards: ProceV |ProcStarIV | ProceIV | Proc104 | ProcStarIII  | ProceIII 
    ProcWizard | ProcMultiPort | Proc Boards | Proc Daughterboards | ProcHILs | ProcFG

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