GiDEL's PROC_SoC 3 & PROC_SoC 10 System Targets ASIC/ SoC Development Projects of 6 to 180+Million Gates
 

Overview

As a module of the PROC_SoC™ Verification System the PROC_SoC 10™ provides scalability for multiple systems to be interconnected and used to verify SoC designs with 180million+ gates. GiDEL's PROC_SoC 10 is itself a modular and scalable ASIC verification system.

The PROC_SoC 10 module has a rated capacity of up to 60 million ASIC gates.  Fast /Gigabit Ethernet communication combined with GiDEL's development tools, enable users to run regression tests on their ASIC designs and to debug the entire chip design including embedded software across their company's local area network. The PROC_SoC 10 is operated in an in-circuit emulation mode with high performance I/O’s interfaced to a target or prototype system. Real world data and applications software comprise test suites with the system’s debugging tools providing visibility to buses and internal nodes of the design.

Up to ten, 3 million/ 6 million gate, reconfigurable PROC3M / PROC6M boards, each with two, interconnected high speed Stratix II 180 or Stratix III 340 FPGAs, may be in a single PROC_SoC 10 system. Each PROC_SoC 10 module can perform as a single ASIC device at typical system speeds of 35 to 300MHz, or shared to verify different design blocks or small, independent SoC designs.

The PROC_SoC 10’s unique interconnect topology, enables any FPGA to directly connect to any other FPGA in the same PROC_SoC 10 or other PROC_SoC 10s, through up to six interconnections per FPGA of 118 pins each. Additionally there are 261 FPGA-to-FPGA I/O connections on each PROC6M element and 5 global lines connecting all FPGAs.

The system is optimized for speed, eliminating the extra delays inherent within routing switches, and hops through FPGAs and other connection technologies used in legacy systems.

Fast, efficient implementation and debug shortens your project schedules.

Every PROC_SoC 10 module includes the PROC Developer’s Kit. The Kit consists of a suite of tools for the efficient mapping of your chip designs into PROC_SoC 10 systems, and for debugging your design. The PROCWizard™ Software manages these processes and integrates the files generated by best-of-breed tools for partitioning, design mapping, synthesis and place and route. The PROCWizard also generates a unique application driver. For each user's application, it will generate a dedicated driver which is extremely easy to use with optimized performance. This enables fast setup to run comprehensive test benches from a host across a network to the verification system.

The PROC Developer's Kit includes the following:

(1) The PROCWizard Software for configuring and debugging ASIC and ASSP designs in the verification system,
 
(2) PROCMultiPort, PROCMegaFIFO, and PROCMegaDelay IPs, for configuring onboard memory and automatic generation of
     DMA controllers for fast data transfers between the verification hardware and software on the host computer,

(3) PROC_HILs enabling higher level of test-bench design using Simulink, plus

(4) Altera’s Quartus II Software suite for FPGA mapping, synthesis, and place and route of designs into the verification hardware,

(5) Altera’s Ethernet blaster enabling remote access to SignalTap.

Each memory block can have up to 16 ports, each with their own clock domain and data width. PROCMegaFIFO IP provides a fast efficient mechanism to transfer data to/from the PROC_SoC 10 user design and a host computer, or between sub-designs within the PROC_SoC 10 using on board memory as a large FIFO. PROCMegaDelay IP provides a simple mechanism for using on-board memory for large delays used for frame and field delay 3D matrix computation and more.  

This entire reusable system enables you to focus on your proprietary value-added design, and not spend your valuable months of effort to create verification platforms that are unique to a specific project.

PROC_SoC 3 system offers the same features as the PROC_SoC 10 but for smaller application requires 3/ 6 million to 9/ 18 million ASIC gates.