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The concept:
This is an expandable, building-block type system. Multiples of the largest,
reasonable FPGAs are utilized on a board. By using ultra high-performance 12 GHz connectors with shielded signals,
and thousands of ground connection pins, we ensure that this multiple board system performs
electrically as if it is one board. Furthermore, due to its physical structure;
the traces between the devices are shorter, providing a minimal connection delay.
The PROCSuperStarTM
offers an incredible improvement in time-to-market, because it eliminates the need for board design,
the PCI application driver, board constrains and a memory controller.
This enables designers to focus on their proprietary value-added design and
not spend their valuable effort to re-create standard design components.
Equipment reuse:
The PROCSuperStar system had been designed for
optimally reuse the hardware.
You may use several boards independently as sub design verification, system test and software
development.
Then, as the project progress, you may gather some boards together and build the hole system.
After there is no need for the hole system to the project you may spade the boards among other projects.
This way, the equipment you by for the peak project will be fully reuse.
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Key features:
- Supported by Gidel’s PROC Developer’s Kit.
- Up to 21 ALTERA® Stratix® 80 FPGAs in a simple system.
- 1,659,840 logic elements.
- Up to 3,696 dedicated high speed multipliers.
- 148M bit of distributed, small memories within the FPGA devices.
Total memory bandwidth up to 4,231GB/s
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- Up to 16,107 M512 RAM blocks (32 x 18 bits).
- Up to 7,644 M4K RAM blocks (128 x 36 bits).
- Up to 189 MegaRAM blocks (4K x 144 bits).
- 448MB DRAM with unique controller. May be divided logically up to 224 external memories per system.
- System clock speed up to 200Mhz.
- 2,778 fast I/Os for System daughter boards.
- Hundreds of connections between FPGA’s. May be used as one big system or as several systems with medium rang capacity.
- Modular system, enables optimal reuse.
- 2 internal / external clocks that drive all of the system.
- Up to 24 output clocks and 48 input clocks for daughter board’s connections.
- Up to 252 PLL’s with up to 1008 internal Clock domains.
- Direct PCI connection and stand-Alone operating modes.
- MultiVolt I/O. User may select VCCIO and I/O protocols connecting the FPGAs and
the Daughter boards.
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